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?1 cxp834p16 cxp834p17 e93z14b63-st cmos 8-bit single chip microcomputer description the cxp834p16 and cxp834p17 are a cmos 8-bit microcomputer which consists of a/d converter, serial interface, timer/counter, time base timer, 32khz timer/counter, lcd controller/driver, remote control receiving circuit and pwm output, as well as basic configurations like 8-bit cpu, prom, ram and i/o port. they are integrated into a single chip. also cxp834p16 and cxp834p17 provide sleep/ stop function which enables to lower power consumption. the cxp834p16 and cxp834p17 are the prom- incorporated version of the cxp83416 and cxp83417 with built-in mask rom. these provide the additional feature of being able to write directly into the program. thus, they are most suitable for evaluation use during system development and for small-quantity production. features a wide instruction set (213 instructions) which covers various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 400ns at 10mhz operation (4.5 to 5.5v) 122s at 32khz operation (2.7 to 5.5v) incorporated prom capacity 16k bytes incorporated ram capacity 448 bytes (lcd display data area included) peripheral functions ?a/d converter 8 bits, 8 channels, successive approximation system (conversion time: 32s/10mhz) ?serial interface incorporated 8-bit and 8-stage fifo (1 to 8 bytes auto transfer), 1 circuit 2 channels timer 8-bit timer, 8-bit timer/counter, 19-bit time base timer, 32khz timer/counter ?lcd controller/driver maximum 128 segments display possible (during 1/4 duty) 4 common outputs, 32 segment outputs display method: static, 1/2, 1/3 and 1/4 duty bias method: 1/2 and 1/3 bias ?remote control receiving circuit 8-bit pulse measurement counter 6-stage fifo ?pwm output 14 bits 1 channel, 8 bits 1 channel interruption 12 factors, 12 vectors, multi-interruption possible standby mode sleep/stop package 80-pin plastic qfp/lqfp structure silicon gate cmos ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxp834p16 80 pin qfp (plastic) 80 pin lqfp (plastic) cxp834p17 80 pin qfp (plastic)
?2 cxp834p16, cxp834p17 xtal 14bit pwm generator remocon serial interface unit 0 8bit timer/counter 0 8bit timer 1 fifo fifo interrupt controller spc700 cpu core prom 16k bytes prescaler/ time base timer 32khz timer/counter ram 448 bytes 8 an0 to an7 pwm0 rmc si0 so0 si1 so1 ec cs0 sck0 sck1 int0 int1 int2 nmi/int3 tex tx extal v dd vss port c 8 pc0 to pc7 port h 1 ph0 port b 8 pb0 to pb7 port e 5 2 pe0 to pe4 pe5 to pe6 2 32 seg0 to seg31 4 com0 to com3 v l v lc1 v lc2 port a 8 pa0 to pa7 port d 8 pd0 to pd7 port f 8 pf0 to pf7 v lc3 adj pwm1 8bit pwm generator cs1 to clock generator/ system control rst vpp 2 a/d converter lcd controller/ driver 2 block diagram
?3 cxp834p16, cxp834p17 pin assignment (top view) cxp834p16 (qfp package) pe3/int3/nmi pe4/rmc pe5/pwm0 pe6/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/pwm1 pa0/an0 pa1/an1 pa2/an2 pd6/seg22 pd5/seg21 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com3 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal v ss v l v lc3 v lc2 v lc1 com0 com1 com2 pe2/int2 pe1/int1 pe0/int0/ec pf7/seg31 pf6/seg30 vpp tex tx v dd pf5/seg29 pf4/seg28 pf3/seg27 pf2/seg26 pf1/seg25 pf0/seg24 pd7/seg23 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 note) vpp (pin 75) is always connected to v dd .
?4 cxp834p16, cxp834p17 pe5/pwm0 pe6/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/pwm1 pa0/an0 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal v ss v l v lc3 v lc2 v lc1 com0 com1 com2 com3 seg0 pe4/rmc pe3/int3/nmi pe2/int2 pe1/int1 pe0/int0/ec pf7/seg31 pf6/seg30 vpp tex tx v dd pf5/seg29 pf4/seg28 pf3/seg27 pf2/seg26 pf1/seg25 pf0/seg24 pd7/seg23 pd6/seg22 pd5/seg21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 pin assignment (top view) cxp834p16 (lqfp package) note) vpp (pin 73) is always connected to v dd .
?5 cxp834p16, cxp834p17 pe5/pwm0 pe6/to/adj pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 ph0/pwm1 pa0/an0 pd4/seg20 pd3/seg19 pd2/seg18 pd1/seg17 pd0/seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 pa1/an1 pa2/an2 pa3/an3 pa4/an4 pa5/an5 pa6/an6 pa7/an7 rst extal xtal v ss v l v lc3 v lc2 v lc1 com0 com1 com2 com3 seg0 pe4/rmc pe3/int3/nmi pe2/int2 pe1/int1 pe0/int0/ec pf7/seg31 pf6/seg30 vpp tex tx v dd pf5/seg29 pf4/seg28 pf3/seg27 pf2/seg26 pf1/seg25 pf0/seg24 pd7/seg23 pd6/seg22 pd5/seg21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 40 39 38 37 36 35 34 31 32 33 70 69 68 67 65 66 71 72 73 74 75 76 77 78 79 80 1 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 63 64 61 62 pin assignment (top view) cxp834p17 (qfp package) note) vpp (pin 73) is always connected to v dd .
?6 cxp834p16, cxp834p17 pin description symbol i/o functions i/o/analog input pa0/an0 to pa7/an7 (port a) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) analog inputs to a/d converter. (8 pins) i/o pc0 to pc7 (port c) 8-bit i/o port. i/o can be set in a unit of single bits. capable of driving 12ma sync current. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) i/o/output ph0/pwm1 (port h) 1-bit i/o port. incorporation of pull-up resistor can be set through the software. (1 pin) 8-bit pwm output. input/input/input input/input input/input input/input/input input/input output/output output/output/ output pe0/int0/ec pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc pe5/pwm0 pe6/to/adj (port e) 7-bit port. lower 5 bits are for inputs; upper 2 bits are for outputs. (7 pins) external interruption request input. (4 pins) remote control receiving circuit input. 14-bit pwm output. rectangular wave output for 8-bit timer/ counter and 32khz oscillation frequency divider output. i/o/input i/o/input i/o/i/o i/o/input i/o/output i/o/i/o i/o/input i/o/output pb0/cs1 pb1/cs0 pb2/sck0 pb3/si0 pb4/so0 pb5/sck1 pb6/si1 pb7/so1 (port b) 8-bit i/o port. i/o can be set in a unit of single bits. incorporation of pull-up resistor can be set through the software in a unit of 4 bits. (8 pins) chip select input for serial interface (ch1). chip select input for serial interface (ch0). serial clock i/o (ch0). serial data input (ch0). serial data output (ch0). serial clock i/o (ch1). serial data input (ch1). serial data output (ch1). external event inputs for timer/counter. non-maskable intrruption request input.
?7 cxp834p16, cxp834p17 symbol i/o functions output/output pd0/seg16 to pd7/seg23 (port d) 8-bit output port. (8 pins) lcd segment signal output. (16 pins) output/output pf0/seg24 to pf7/seg31 (port f) 8-bit output port. (8 pins) output output output seg0 to seg15 com0 to com3 v lc1 to v lc3 v l input crystal connectors for system clock oscillation. when the clock is supplied externally, input to extal; opposite phase clock should be input to xtal. extal output xtal input crystal connectors for 32khz timer/counter clock generation circuit. for usage as event counter, connect clock oscillation source to tex, and leave tx open. tex output tx input low-level active, system reset. rst positive power supply for the on-chip programmable prom; connect to v dd for normal operation. vpp positive power supply. v dd gnd. vss lcd segment signal output. lcd common signal output. lcd bias power supply. control pin to cut off the current flowing to external lcd bias resistor during standby.
?8 cxp834p16, cxp834p17 data bus rd (port b) aaa aaa aa aa port b direction ip aa aa aaa port b data "0" when reset "0" when reset * schmitt input cs1 cs0 si0 si1 * pull-up transistors approx. 100k w aaa aaa pull-up resistor port b 8 pins hi-z hi-z when reset pa0/an0 to pa7/an7 pb0/cs1 pb1/cs0 pb3/si0 pb6/si1 port b 4 pins 2 pins hi-z pb2/sck0 pb5/sck1 data bus rd (port a) aaaa aa port a direction ip aa aa aaaa aaaa port a data aaaa aaaa pull-up resistor aaaa port a input selection input protection circuit "0" when reset "0" when reset "0" when reset input multiplexer a/d converter * pull-up transistors approx. 100k w * i/o circuit format for pins port a pin circuit format data bus rd (port b) aa ip aa aa aaaa port b output selection "0" when reset * schmitt input sck in aaaa aaaa port b data aaaa aaaa port b direction "0" when reset "0" when reset sck out output enable * pull-up transistors approx. 100k w aaaa aaaa pull-up resistor
?9 cxp834p16, cxp834p17 2 pins hi-z hi-z pin when reset circuit format pb4/so0 pb7/so1 pc0 to pc7 8 pins 5 pins hi-z pe0/int0/ec pe1/int1 pe2/int2 pe3/int3/nmi pe4/rmc aa aa ip aa aa schmitt input rd (port e) data bus int0/ec int1 int2 int3/nmi rmc data bus rd (port c) aaaa aa port c direction ip aa aa aaaa aaaa port c data "0" when reset "0" when reset * 2 * 1 * 2 pull-up transistors approx. 100k w * 1 large current 12ma aaaa aaaa pull-up resistor data bus rd (port b) aa ip aa aa aaaa port b output selection "0" when reset * aaaa aaaa port b data aaaa aaaa port b direction "0" when reset so output enable * pull-up transistors approx. 100k w aaaa aaaa pull-up resistor "0" when reset port e port c port b
?10 cxp834p16, cxp834p17 1 pin high level pin when reset circuit format pe6/to/adj pe5/pwm0 * 1 * 2 port e data "1" when reset port e output selection (upper) mpx port e output selection (lower) adj2k adj16k to internal reset signal * 1 pull-up transistors approx. 150k w . adj signals are frequency divider outputs for 32khz oscillation frequency adjustment. adj2k provides usage as buzzer output. * 2 to output enable port e 1 pin hi-z ph0/pwm1 data bus rd (port h) aa aa ip aa aa aaaa aaaa port h data "0" when reset * aaaa aaaa port h direction "0" when reset * pull-up transistors approx. 100k w aaaa aaaa pull-up resistor aaaa port h output selection pwm1 "0" when reset port h 1 pin port e data bus rd (port e) aa aa aaaa aaaa port e output selection pwm0 aaaa aaaa port e data "0" when reset "1" when reset high level with approx. 150k resistor when reset ()
?11 cxp834p16, cxp834p17 16 pins v dd level pin when reset circuit format seg0 to seg15 v ch v cl segment output (v dd level) pd0 to pd7 pf0 to pf7 pd7 to pd4 pd3 to pd0 pf7 to pf0 port data port/segment output selection segment data by a bit unit by 4-bit unit "0" when reset segment driver aa aa port d port f 4 pins v dd level com0 to com3 v cl1 v cl2 v dd v cl3 common 24 pins segment 1 pin hi-z v l lcd control (dsp bit) "0" when reset aa aa
?12 cxp834p16, cxp834p17 2 pins oscillation pin when reset circuit format extal xtal aa aa ip aa extal xtal ?diagram shows circuit composition during oscillation. ?feedback resistor is removed during stop, and xtal becomes "high" level. a ip 2 pins oscillation tex tx aa aa ip aa tex ?digram shows circuit composition during oscillation. a ip ?when the operation of the oscillation circuit is stopped by the software, the feedback resistor is removed and tex and tx become "low" level and "high" level respectively. tx 1 pin low level rst aa aa aa aa ip schmitt input pull-up resistor mask option op
?13 cxp834p16, cxp834p17 * 1 v in and v out must not exceed v dd + 0.3v. * 2 the large current drive transistor is the n-ch transistor of port c (pc). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should be conducted under the recommended operating conditions. exceeding these conditions may adversely affect the reliability of the lsi. supply voltage lcd bias voltage input voltage output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd vpp v lc1 , v lc2 , v lc3 v in v out i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 ?.3 to +13.0 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ?.3 to +7.0 * 1 ? ?0 15 20 100 ?0 to +75 ?5 to +150 600 380 380 v v v v v ma ma ma ma ma ? ? mw mw mw incorporated prom output (value per pin) total for all output pins all pins excluding large current output (value per pin) large current outputs (value per pin * 2 ) total for all output pins qfp-80p-l01 lqfp-80p-l01 qfp-80p-l03 item symbol rating unit remarks absolute maximum ratings (vss=0v reference)
?14 cxp834p16, cxp834p17 * 1 high-speed mode is 1/2 frequency divider clock selection; low-speed mode is 1/16 frequency divider clock selection. * 2 value for each pin of normal input ports (pa, pb4, pb7, pc and ph0). * 3 value of the following pins: rst, cs0, cs1, si0, si1, sck0, sck1, ec/int0, int1, int2, nmi/int3, and rmc. * 4 specifies only during external clock input. * 5 optimal values are determined by lcd used. * 6 vpp and v dd should be set to the same voltage. high level input voltage low level input voltage operating temperature supply voltage lcd bias voltage 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.4 +75 v v v v v v v ? v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 vss 0.7v dd 0.8v dd v dd ?0.4 0 0 ?.3 ?0 v lc1 v lc2 v lc3 v ih v ihs v ihex v il v ils v ilex topr high-speed mode guaranteed operation range * 1 low-speed mode guaranteed operation range * 1 guaranteed operation range with tex clock guaranteed data hold range during stop * 6 lcd power supply range * 5 * 2 hysteresis input * 3 extal * 4 * 2 hysteresis input * 3 extal * 4 v dd vpp recommended operating conditions (vss=0v reference) vpp = v dd v
?15 cxp834p16, cxp834p17 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 ?.78 v v v v v v ? ? ? ? ? ? ? k k pc pa, pb, pc, pd * 1 , pe5, pe6, pf, ph0, v l (v ol only) extal tex rst * 2 item symbol pins conditions min. v dd i dd1 i il i ih i iz i dd2 i dds1 i dds2 i dds3 v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current 3 5 typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 ?5 ?0 5 15 max. unit dc characteristics electrical characteristics (ta = ?0 to +75?, vss = 0v reference) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, 10mhz crystal oscillation (c 1 = c 2 = 15pf) v dd = 3v, 32khz crystal oscillation (c 1 = c 2 = 47pf) v dd = 5.5v, termination of 10mhz and 32khz crystal oscillation supply current * 4 v dd = 5.5v, v il = 0.4v v dd = 4.5v, v ih = 4.0v v dd = 5.5v, v i = 0, 5.5v v dd = 5v, v lc1 = 3.75v v lc2 = 2.5v v lc3 = 1.25v high-speed mode operation (1/2 frequency divider clock) sleep mode stop mode i/o leakage current r com common output impedance r seg segment output impedance pa to pc * 3 , ph * 3 , pe0 to pe4, rst * 2 com0 to com3 seg0 to seg15, seg16 to seg31 * 1 40 1000 8 30 30 18 400 1.1 9 ma ? ma ? ?
?16 cxp834p16, cxp834p17 item symbol pins conditions min. pa to pc, pe1 to pe4, extal, tex, rst clock 1mhz 0v for all pins excluding measured pins c in typ. max. unit * 1 common pins of pd0/seg16 to pd7/seg23, pf0/seg24, pf7/seg31, pd and pf are the case when the common pin is selected as port; seg16 to seg31 is when the common pin is selected as segment output. * 2 rst specifies the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. * 3 pa to pc, and ph0 specify the input current when pull-up resistor has been selected; leakage current when no resistor has been selected. (pe0 to pe4 specify the leakage current.) * 4 when all output pins are left open. input capacity pf 20 10
?17 cxp834p16, cxp834p17 * t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control registor (clc: 00fe h ). t sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") extal t xh t xl t cf t cr 0.4v v dd ?0.4v 1/fc aaaa a aa a aaaa aaaa a aa a aaaa crystal oscillation ceramic oscillation extal xtal external clock extal xtal 74hc04 c 1 c 2 aaaa a aa a aaaa 32khz clock applied condition crystal oscillation tex tx c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall time event count input clock pulse width event count input clock rise and fall time system clock frequency event count input clock input pulse width event count input clock rise and fall time f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal extal extal ec ec tex tx tex tex mhz ns ns ns ms khz ? ms item symbol pin conditions min. unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 1 37.5 t sys+50 * 10 typ. 32.768 max. 10 200 20 20 (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 2. clock applied conditions fig. 1. clock timing tex ec t eh t el t ef t er 0.2v dd 0.8v dd t th t tl t tf t tr fig. 3. event count clock timing
?18 cxp834p16, cxp834p17 (2) serial transfer (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 ? sck0 (cs1 ? sck1) delay time cs0 -? sck0 (cs1 -? sck1) floating delay time cs0 ? so0 (cs1 ? so1) delay time cs0 -? so0 (cs1 -? so1) floating delay time cs0 (cs1) high level width sck0 (sck1) cycle time sck0 (sck1) high and low level widths si0 (si1) input setup time (for sck0 - (sck1 - ) ) si0 (si1) input hold time (for sck0 - (sck1 - ) ) sck0 ? so0 (sck1 ? so1) delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 (sck1) sck0 (sck1) so0 (so1) so0 (so1) cs0 (cs1) sck0 (sck1) sck0 (sck1) si0 (si1) si0 (si1) so0 (so1) input mode output mode input mode output mode sck0 (sck1) input mode sck0 (sck1) output mode sck0 (sck1) input mode sck0 (sck1) output mode sck0 (sck1) input mode sck0 (sck1) output mode ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit chip select transfer mode (sck0 (sck1) = output mode) chip select transfer mode (sck0 (sck1) = output mode) chip select transfer mode chip select transfer mode chip select transfer mode conditions note 1) t sys indicates the three values below according to the upper two bits (cpu clock selection) of the clock control register (clc: 00fe h ). t sys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") note 2) the load condition for the sck0 (sck1) output mode, so0 (so1) output delay time is 50pf + 1ttl.
?19 cxp834p16, cxp834p17 fig. 4. serial transfer ch0 timing cs0 (cs1) sck0 (sck1) 0.2v dd 0.8v dd t whcs t dcsk t dcskf 0.8v dd 0.2v dd 0.8v dd t kcy t kl t kh 0.8v dd 0.2v dd si0 (si1) t sik t ksi input data t dcso t kso t dcsof output data 0.8v dd 0.2v dd so0 (so1)
?20 cxp834p16, cxp834p17 conversion time sampling time analog input voltage t conv t samp v ian v zt * 1 v ft * 2 an0 to an7 ta = 25? v dd = 5.0v v ss = 0v linearity error zero transition voltage full-scale transition voltage resolution ? ? v v dd + 0.3 160/f adc * 3 12/f adc * 3 0 item symbol pin conditions min. typ. max. unit bits (3) a/d converter characteristics (ta = ?0 to +75?, v dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = 0v reference) 8 3 lsb 70 mv 5030 10 4970 ?0 4910 mv fig. 5. definition of a/d converter terms analog input linearity error v ft v zt 00 h 01 h fe h ff h digital conversion value * 1 v zt : value at which the digital conversion value changes from 00 h to 01 h and vice versa. * 2 v ft : value at which the digital conversion value changes from fe h to ff h and vice versa. * 3 f adc indicates the below values due to the contents of bit 6 (ck3) of the a/d control registor (adc: 00f9 h ) and bit 7 (pck1) and bit 6 (pck0) of the clock control registor (clc: 00fe h ) 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = fc/2 f adc = fc/4 f adc = fc/16 f adc = fc f adc = fc/2 f adc = fc/8 cks pck1, pck0 0 ( f /2 selection) 0 ( f selection)
?21 cxp834p16, cxp834p17 external interruption high and low level widths reset input low level width int0 int1 int2 nmi/int3 rst 1 32/fc ? ? item symbol pin conditions min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75?, v dd = 4.5 to 5.5v, vss = 0v reference) 0.2v dd 0.8v dd t ih t il t il t ih int0 int1 int2 nmi/int3 (nmi is specified only for the falling edge) fig 6. interruption input timing t rsl 0.2v dd rst fig. 7. rst input timing
?22 cxp834p16, cxp834p17 appendix fig. 8. spc700 series recommended oscillation circuit c 1 aaaa a aa a aaaa extal xtal c 2 rd aaaa a aa a aaaa extal xtal (i) main clock aaaa a aa a aaaa extal xtal c 1 c 2 rd xtal (ii) main clock aaaaa a aaa a aaaaa extal xtal c 1 c 2 rd aaaaa a aaa a aaaaa tex tx (iii) sub clock manufacturer murata mfg co., ltd. river eletec co., ltd. kinseki ltd. model csa4.19mg csa8.00mg cst4.19mgw * cst8.00mtw * hc-49/u03 hc-49/u (-s) fc (mhz) 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 4.19 8.00 10.00 18 18 30 15 22 30 15 22 0 2.2k 470 560 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) csa10.0mt (ii) cst10.00mtw * (i) models with an asterisk ( * ) have the built-in ground capacitance (c 1 , c 2 ). product list optional package rom capacity reset pin pull-up resistance 80-pin plastic qfp/lqfp 80-pin plastic qfp (0.65mm pitch) 80-pin plastic qfp 80-pin plastic lqfp 80-pin plastic qfp (0.65mm pitch) mask cxp83412 12k bytes existent/non-existent existent 16k bytes 12k bytes 16k bytes prom 16k bytes cxp83416 cxp83413 cxp83417 cxp834p16q-1- prom cxp834p16r-1- CXP834P17Q-1-
?23 cxp834p16, cxp834p17 package outline unit: mm cxp834p16 cxp834p16 package structure sony code eiaj code jedec code qfp-80p-l01 * qfp080-p-1420-a package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 1.6g 23.9 0.4 20.0 ?0.1 + 0.4 1 80 65 64 41 40 25 24 0.8 0.35 ?0.1 + 0.15 14.0 ?0.1 + 0.4 17.9 0.4 16.3 0.1 ?0.05 + 0.2 2.75 ?0.15 + 0.35 0.8 0.2 0.15 ?0.05 + 0.1 80pin qfp (plastic) m 0.12 0.15 0?to 10 detail a a sony code eiaj code jedec code package material lead treatment lead material package weight epoxy / phenol resin solder plating 42 alloy package structure 14.0 0.2 * 12.0 0.1 (0.22) 60 41 40 21 20 80 61 1 0.5 0.08 0.18 ?0.03 + 0.08 a 1.5 ?0.1 + 0.2 0.127 ?0.02 + 0.05 0.5 0.2 (13.0) 0.1 0.1 0.5 0.2 0?to 10 detail a 80pin lqfp (plastic) 0.5g lqfp-80p-l01 * qfp080-p-1212-a 0.1 note: dimension * ?does not include mold protrusion.
?24 cxp834p16, cxp834p17 cxp834p17 sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy qfp-80p-l03 lqfp080-p-1414 0.6g 80pin qfp (plastic) 16.0 0.4 14.0 ?0.1 + 0.4 0.65 0.3 ?0.1 + 0.15 0?to 10 0.5 0.2 0.1 ?0.1 + 0.15 (15.0) 0.127 ?0.05 + 0.1 1.5 ?0.15 + 0.35 40 21 20 1 41 60 61 80 m 0.12 0.1

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